#ifndef _UDP_STRUCT_H
#define _UDP_STRUCT_H

#define DATA_BUFSIZE     		   992 // 0x3E0
#define FRAME_START_OFFSET         0    //(0x0)
#define SEQUENCE_OFFSET            2    //(0x2)
#define CONTENT_LENGTH_OFFSET      4    //(0x4)
#define BOARD_IP3_OFFSET           6    //(0x6)
#define BOARD_IP4_OFFSET           7    //(0x7)
#define DEST_PORT_OFFSET           8    //(0x8)
#define SW_VER_FPGA_OFFSET         10   //(0xA)
#define SW_VER_PPC440_OFFSET       11   //(0xB)
#define SYSTEM_ID_OFFSET           12   //(0xC)
#define CAB_BOX_ID_OFFSET          13   //(0xD)
#define BACKUP1_OFFSET             14   //(0xE)
#define BACKUP2_OFFSET             15   //(0xF)
#define MODULE_FAN_BIT_OFFSET      16   //(0x10)
#define MODULE_PWR1_BIT_OFFSET     48   //(0x30)
#define MODULE_IIC1_BIT_OFFSET     144  //(0x90)
#define FRAME_END_OFFSET           976  //(0x3D0)
#define FRAME_END_BYTE_SIZE        16

#define MODULE_START_OFFSET        0X10
#define MODULE_END_OFFSET          0X3D0

#define SEND_IP1      230
#define SEND_IP2      3
#define SEND_IP3      18
#define SEND_IP4      6

#define SYSTEM_ID    0x06



#define MODULE_ID_SYSCTL           0x01
#define MODULE_ID_POWER            0x02
#define MODULE_ID_FAN              0x03
#define MODULE_ID_HR14V1           0x04
#define MODULE_ID_DIR9V1           0x05
#define MODULE_ID_VPX6_FSP2        0x06
#define MODULE_ID_VPX6_FSP2_4800   0x07
#define MODULE_ID_SW_GEN1          0x08
#define MODULE_ID_SW_GEN2          0x09
#define MODULE_ID_FV74V1           0x0A
#define MODULE_ID_FV74A1           0x0B
#define MODULE_ID_BFM2V1           0x0C
#define MODULE_ID_BFM3V1           0x0D
#define MODULE_ID_PC14V1           0x0E
#define MODULE_ID_VQ40_1           0x0F
#define MODULE_ID_HR11V1           0x10
#define MODULE_ID_VPX_RECORD       0x11
#define MODULE_ID_SWIF             0x12

#define NETIF_IP1     192
#define NETIF_IP2     168
#define NETIF_IP3     168
#define NETIF_IP4 	  133

#endif
